The present invention pertains to the electronic signal processing art and, in particular, to a programmable frequency counter.
Programmable frequency counters have been well known in the electronic processing art, particularly in the frequency synthesizer field. Frequency synthesizers commonly employ standard phase lock loop circuitry wherein a reference frequency oscillator signal may be divided by a selected one of a plurality of divisors thus providing an output signal of desired frequency. Previous techniques employed in digital frequency synthesizers have used, in the feedback portion of a conventional phase lock loop, a variable prescaler, and first and second counters. The first counter has been programmable and is used to divide the output of the variable prescaler by a fixed number (N). The second counter, often referred to as a swallow counter, has been used to switch the variable prescaler to a new divisor, or modulus, which new modulus is present during the counting of "N". As is discussed at page 10-3 of the Motorola "McMOS HANDBOOK", printed 1974 by Motorola, Inc., the total divisor N.sub.T of the feedback loop is given by: EQU N.sub.T = (P + 1)A + P(N - A)
where, the variable modulus prescaler operates between two divisors P and P+1, the swallow counter has a fixed divisor A, and the programmable divider has the divisor N.
While the above described frequency synthesizer provided the desired function, it requires a large number of parts and thus is expensive to manufacture. It is desirable, therefore, to provide the frequency synthesizer function using fewer parts.